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Module outline UFEEHH-30-2:
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This module provides an introduction to the use of the hardware description language, VHDL, along with an introduction to the architecture of microprocessors from a hardware designers perspective. We will cover the subset of VHDL that is used for synthesis with some reference to the use of the language for the behavioural modelling of hardware systems.
Your understanding and use of state-machines will be extended and the concept of a datapath-controller model introduced and developed. A series of problems will be explored culminating in the design, simulation,testing and, hopefully, implementation of a simple 8 bit microprocessor.
The design of the microprocessor control unit will be investigated in some detail with three distinct approaches being covered.
This module makes intensive use of the development tools from Alliance and will introduce you to other industry standard tools as well.
Most of the examples provided come from one of three sources: the recommended course texts, the documentation provided with the Alliance toolkit, or locally.
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Unfortunately there is no single textbook that covers all the material in this module. A study pack of key material is in development and will be made available via the Frenchay Campus Library. In the meantime key material is to be found in the following books. The first 2 provide excellent coverage of VHDL in digital design as well as examples of implementing a CPU in VHDL. The third book has excellent coverage of the design issues in developing a CPU but minimal coverage of VHDL.
I strongly recommend Digital Design (VHDL), Ashenden, P
An alternative recommended text for VHDL is Digital System Design with VHDL, Zwolinski, M. You should read chapters 3 - 7 at a minimum.
Computer Systems, Organization & Architecture, Carpinelli, J., Addison-Wesley. Ideally you should read chapters 3, 5 - 8, 10. At the very least read chapter 6. This book is rather expensive but there are copies in the Bolland Library.
Blackwell reading list and bookshop availability.
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For free books (provided you return them on time) on all aspects of VHDL and digital design, use the Library. A selection of suggested reading is given here.
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Examples are taken/modified from the recommended course texts
A short article on ASM (in postscript) from Circuit Cellar Magazine.
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Laboratory worksheets & Exercises :
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A brief note for those of you using Ubuntu at home or on your laptop and want to install the Alliance toolkit
- 1) install a proper version of GNU/Linux (only joking[ish])
- 2) You will probably need to install a C compiler
- 3) Then compile the alliance toolkit from source as follows. With thanks to Graham Petley for this, posted on the alliance mailing list.
I found some issues with version 4.3 of gcc.
You can install version 4.2 from Synaptic.
The configure options I used are
--prefix=/home/cad/alliance\
--without-xpm-libraries /
CXX=g++-4.2 CC=gcc-4.2
The prefix is because I install the s/w
to the home partitionwhich is protected when
OS upgrades are done. I am using Ubuntu 9.04.
Use them well. Note that each lab will require several weeks work. You will find it very useful to read the Alliance tools overview in conjunction with the exercises.
- Lab 1 :
- Worksheet 0 on using the editor. It is essential that you do this worksheet. You might need to follow the instructions below (new start-up script) if your .emacs file doesn't look like the example in the worksheet.
- New start-up script to make things easier here, save in your home folder (NOT the DESKTOP!), then follow the instructions below or ask for help
- On a command line type
- cd; chmod 700 setup_script.sh
- ./setup_script.sh
- emacs dummy.vhd
- it should say 'vhdl mode' on a bar at the bottom of the editor.
- Worksheet 1 introducing the tools and a little of the language.
- Worksheet 2 introducing a little more of the language.
- Lab 2 :
- Alliance toolchain (note, some of the issues referred to have been resolved), simple state machines worksheet in VHDL. Note that the path to the examples refered to in the worksheet is temporarily here and here
- Lab 3 :
- Datapath-controller development problem.
- Using the traffic-lights worksheet as your specification: implement a controller which will manage a set of timers.
- You should use ASM notation for your design.
- Implement and test the controller.
- Implement the timer(s).
- Combine them into a top level design.
- Verify your top level design.
- Modify to run on a Lattice board. See Lab 4 for this.
- Lab 4:
- You will need to access the Lattice synthesis tools using these instructions .
- Converting EDIF files from Alliance names to Lattice names. Note that the tools referred to in this worksheet are now in the $ALLIANCE_TOP/bin directory. The man page for sxconv should also now be in the standard search path for man pages. You only need to actually do section 4 of this worksheet, but you should read the rest.
- Downloading to the Lattice isp evaluation board. Revised version. Schematic (scanned gif) for the evaluation board.
- Lab 5 ... Implementation of CPU as per assignment specification
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Worksheets for Labs & related support material:
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- Lab exercise related
- Old version of the lab1 worksheets
NOTE: There is an error on page 5 of the worksheet; labels in pattern file may not include the _ character.
- Converting Alliance EDIF to Lattice EDIF
- Lattice evaluation board worksheet. To be revised.
- Alliance 5.0 toolkit overview. Use with lab2s' worksheet.
- Misc. VHDL
- Thunderbird lights outline sum of products state machine in vhdl.
- synchronous downcounter with load. Demonstrates use of generics and functions.
- rw_buf fsm model for use with lab2 worksheet.
- rw_buf pattern file for use with lab2 worksheet.
- Behavioural model of a toggle flip-flop showing use of variables in VHDL.
- Discussion of state value assignment using the toll booth example.
- Emacs support worksheets
- Misc Support Worksheets
- RCS worksheet...(also under construction)
- tar related worksheet if you're stuck unpacking the Alliance stuff
- example shell script for running the alliance toolchain
D-type flipflop worksheet exploring timing issues.
Overview of delta delay in simulation
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Code and Pattern examples:
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Answers to last years paper
Other stuff
It can sometimes be easier to use the genpat utility to create large pattern files. You write a 'C' program using special function calls to create the pattern file. This file is then read by genpat. Here is example code for pattern file generation. This example is for the cpu controller and can be extended or modified to suit your design.
man genpat for details, also each function has its own page, (case sensitive, the function names are upper-case)
Cpu instruction test pattern example. Monitors internal CPU signals, edit to suit your signal names.
Support files for an SBC version of the RS_CPU, edit to suit your design. The top level model includes the address decoding logic to suit the memory map described in the ROM file.
A selection of alternative CPU designs that you might like to have a look at.
- The Parwan CPU from Navabi's book refered to above.
- The Apollo Guidance computer. Fly to the Moon and back on a 12k ROM based system.
- The gumnut processor documented in Ashenden's book, see above for book details or here for the books companion site
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Bus protocols
References to the various bus protocols mentioned in the lecture.
- Overview of all the buses discussed.
- IBM's CoreConnect protocol
- The avalon bus protocol from Altera. Search for avalon on the site, the details are in a large document (106 pages).
- The wishbone spec is at the Opencores site.
- The Arm AMBA bus protocols.
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Hints'n'tips on setting up your environment in the lab
'dot emacs'
Additions to setup vhdl mode for the Alliance toolkit file extensions. Copy and paste the following into your .emacs file :-
(autoload 'vhdl-mode "vhdl-mode" "VHDL Editing Mode" t)
(setq auto-mode-alist
(append
'(("\\.vhd$" . vhdl-mode)
("\\.vbe$" . vhdl-mode)
("\\.vst$" . vhdl-mode)
("\\.fsm$" . vhdl-mode)
) auto-mode-alist))
To avoid the problem, in 3P28, of Emacs entering 'diff-mode' when opening pattern files (.pat), add the following to your .emacs file:
(autoload 'text-mode "text-mode" "Text Editing Mode" t)
(setq auto-mode-alist
(append
'(("\\.pat$" . text-mode)
) auto-mode-alist))
- Patch for changing background of xpat
patch -i xpat.patch xpat.par
xpat.par is in $ALLIANCE_TOP/etc. save the patch file as plain text and apply. You will need write permission on both the .par file and it's directory.
Alternatively, copy the xpat.par file to your home directory, modify as above and then set the environment variable XPAT_PARAM_NAME to point to the file in your home directory eg
export XPAT_PARAM_NAME=$HOME/xpat.par
Add this to your start-up files (.bashrc / .bash_profile for bash and related shells) to avoid having to set it manually every time you log in.
- Capturing screenshots of patterns etc.
import -rotate -90 -page a4 filename.[ ps | eps | jpeg | png ]
in a terminal and then drag a bounding box to surround the area to be captured. The above will rotate the captured area and fit it to an a4 sized sheet. The output file will be in the format specified by the output file suffix and selected from the list above.
Examples are in a tarball for download. Save this file to a temporary directory, cd into the temporary directory and then type tar -zxvf startups.tar.gz. This will unpack the files and avoid overwriting your existing files. you can then copy the bits that you want into your existing files. Alternatively just cut'n'paste from the browser window :)
There are all sorts of odds'n'ends in the tarball most of which yo probably don't need to worry about at this stage
Also included in the download are a basic .emacs to extend the list of filenames which will trigger vhdl mode and a .bashrc to set up the environment variables for the Alliance toolset amongst other things.
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Sample Q's
here, note that more emphasis will be placed on ASM as a diagramatic representation of state machines this year than in the papers from which the questions are taken.
Reference Material
ASM examples and explanations.
oldish but useful discussion of ASM with FPGA & CPLD emphasis.
Archive of VHDL links, tutorials, software and related material. A good starting point.
Excellent VHDLtutorial site.
Sequence Enumeration : Developing Black Box Specifications
Sequence Enumeration : Soda Machine example.
Rules for the soda machine example
- 1: The soda machine will produce a soda after 75 cents has been entered. The machine will only accept quarters.
- 2: When the "Change Return" button is pressed, the available change in the input tray is returned.
- 3: When there is no more soda in the machine, the "Sold Out" light will be illuminated.
- 4: When the machine is powered on, the "Power On" light will be illuminated.
Derived rules for the soda machine example
- D1: Selecting a soda before the correct change has been entered will result in no response from the soda machine.
- D2: A "Sold Out" stimulus before the last soda is selected will cause the "Sold Out" light to be illuminated.
- D3: Whenever the "Sold Out" light is illuminated, any change deposited into the machine will automatically be returned.
- D4: The soda select button will be ignored whenever the "Sold Out" light is on or whenever correct change has not been received.
isp1016 device data sheet
74LS74 D-type flip-flop data sheet for use with 'd-type' worksheet.
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