You will need the modified ts_7300_usercore.vhd and the modified opencore ts7300 project. This provides a simple example of accessing the I/O pins From the original opencore verilog boilerplate: * There is a 40-pin header next to the FPGA. It is broken up into 2 20 pin * connectors. One is labeled DIO2 and contains the 18 dedicated GPIO pins. The * other contains 17 signals that are used by the TS-VIDCORE but can also be used * as GPIO if video is not used. DO NOT DRIVE THESE SIGNALS OVER 3.3V!!! They * go straight into the FPGA pads unbuffered. * ___________________________________________________________ * | 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 | * | 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 | * \----------------------------------------------------------/ * * Pin 1 is marked with a white dot nearest the vga socket. * Pin 21 is marked with a white dot to the left of the DIO2 label * pins #2 and #22 are grounds * pin #20 is fused 5V (polyfuse) * pin #40 is regulated 3.3V * pin #18 can be externally driven high to disable DB15 VGA connector DACs * pin #36 and #38 also go to the red and green LEDs (active low) * pin #39 is a dedicated clock input and cannot be programmed for output * pins marked * are reserved. * D D D D D D R T + * R R R R R H V * * * I I I I I I X X 3 G E E E E E S S O + G O O O O O O _ _ . N D D D D D Y Y E 5 N 1 1 1 1 1 1 L L 3 D 0 1 2 3 4 N N V V D 0 1 2 3 4 5 D D V ___________________________________________________________ | 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 | | 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 | \----------------------------------------------------------/ B B B B B G G G G G D D D D D D D D D D L L L L L R R R R R I I I I I I I I I I U U U U U N N N N N O O O O O O O O O O 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 5 6 7 8 9 * 40 bits: 1 = I/O enabled Don't output to (use) pins 2,18,20,22,39,40 Hex values to enable each usable pin, names are those used in TS7300 documents. (pin #, pin name, enable val) 1 BLU0 0x0000000001; 4 RED0 0x0000000008; 11 GRN0 0x0000000400 3 BLU1 0x0000000004; 6 RED1 0x0000000020; 13 GRN1 0x0000001000 5 BLU2 0x0000000010; 8 RED2 0x0000000080; 15 GRN2 0x0000004000 7 BLU3 0x0000000040; 10 RED3 0x0000000200; 17 GRN3 0x0000010000 9 BLU4 0x0000000100; 12 RED4 0x0000000800; 19 GRN4 0x0000040000 14 HSYN 0x0000002000; 16 VSYN 0x0000008000 DIO2 ( second part of header, confusingly there's also a pin named DIO2 ) 21 DIO0 0x0000100000; 07 DIO8 0x1000000000; 36 RX_LD 0x0800000000; 23 DIO1 0x0000400000; 39 DIO9 0x4000000000; 38 TX_LD 0x2000000000; 25 DIO2 0x0001000000; 24 DIO10 0x0000800000; 27 DIO3 0x0004000000; 26 DIO11 0x0002000000; 29 DIO4 0x0010000000; 28 DIO12 0x0008000000; 31 DIO5 0x0040000000; 30 DIO13 0x0020000000; 33 DIO6 0x0100000000; 32 DIO14 0x0080000000; 35 DIO7 0x0400000000; 34 DIO15 0x0200000000; 40 pins doesn't map cleanly to multiples of 32 bits so the modified usercore maps some of this as follows: _reg is the output register and holds the last value written to the IO _read is the current value read from the IO pins, only pins configured as input have valid data. vga_reg and vga_read bits 0..4 = BLU0..BLU4, 5..9 = GRN0..GRN4, 10..15 = RED0..RED4 bits 16..31 are invalid , ignored on a write and grabaeg on a read. dio2_reg and dio2_read bits 0..8 = DIO0..DIO8, bit 9 is reserved, bits 10..15 = DIO10..DIO15 bits 16..31 are invalid , ignored on a write and garbage on a read. misc_reg and misc_read bit 0 = HSYN bit 1 = VSYN bit 2 = RX_LD bit 3 = TX_LD bits 4..31 are invalid , ignored on a write and garbage on a read. The registers start from 0x72A00000 which maps to 0x280000 internally in the vhd component. The mapping is different to the way that mem_debug sees things :( -- WRITE CYCLE case addr is when x"280000" => vga_reg <= wb_dat_i(14 downto 0); when x"280001" => vga_enable <= wb_dat_i(14 downto 0); when x"280002" => dio2_reg <= wb_dat_i(15 downto 0); when x"280003" => dio2_enable <= wb_dat_i(15 downto 0); when x"280004" => misc_reg <= wb_dat_i(3 downto 0); when x"280005" => misc_enable <= wb_dat_i(3 downto 0); when others => null; end case; end if; -- READ CYCLE case addr is when x"280000" => dummyreg <= "00000000000000000" & vga_read; when x"280001" => dummyreg <= "00000000000000000" & vga_enable; when x"280002" => dummyreg <= "0000000000000000" & dio2_read; when x"280003" => dummyreg <= "0000000000000000" & dio2_enable; when x"280004" => dummyreg <= "0000000000000000000000000000" & misc_read; when x"280005" => dummyreg <= "0000000000000000000000000000" & misc_enable; when others => dummyreg <= x"deadbeef"; end case; 0xDEADBEEF is nice and easy to spot in memory dumps :)