library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity divcount is

  generic (
    n : natural := 5);


  port (
    clk     : in  std_logic;
    reset   : in  std_logic;            -- active low
    restart : in  std_logic;            -- active low
    t1      : out std_logic;            -- active high
    t2      : out std_logic;            -- active high
    t3      : out std_logic);           -- active high

end divcount;

architecture rtl of divcount is

  signal count_val              : unsigned(n-1 downto 0);
  signal t1_sig, t2_sig, t3_sig : std_logic;
begin  -- rtl

  -- purpose: model of a n bit up counter with 
  --          3 outputs dependent on different 
  --          count values.
  --          To provide different time intervals
  --          from reset/restart.
  -- type   : sequential
  -- inputs : clk, reset, restart
  -- outputs: t1, t2, t3

  p0 : process (clk)

  begin  -- process

    if (rising_edge(clk)) then
      if reset = '0' or restart = '0' then
        -- to_unsigned(arg, size)
        -- returns vector(size-1 downto 0)
        -- used to set counter to all zeros
        count_val <= to_unsigned(0, n);
        t1_sig    <= '0';
        t2_sig    <= '0';
        t3_sig    <= '0';
      else
        count_val <= count_val + to_unsigned(1, n);  -- increment counter
      end if;
      if count_val(4 downto 0) = "00111" then
        t1_sig <= not t1_sig;                        -- toggle signal
      elsif count_val(4 downto 0) = "10000" then
        t2_sig <= not t2_sig;                        -- toggle signal
      elsif count_val(4 downto 0) = "11101" then
        t3_sig <= not t3_sig;                        -- toggle signal
      end if;
    end if;
  end process p0;

  -- assign outputs
  
  t3 <= t3_sig;
  t2 <= t2_sig;
  t1 <= t1_sig;

end rtl;