library ieee;
use ieee.std_logic_1164.all;
entity tff is

  port (
    t, clk, reset : in  std_ulogic;
    q, qbar       : out std_ulogic);

end tff;

architecture var of tff is

begin  -- var

  -- purpose: variable model of t-type ff
  -- type   : sequential
  -- inputs : clk, reset, t
  -- outputs: q, qbar
  p0               : process (clk)
    variable state : std_ulogic;

  begin  -- process p0
    if clk'event and clk = '1' then     -- rising clock edge
      if reset = '0' then               -- synchronous reset (active low)
        state := '0';
      elsif t = '1' then
        state := not state;
      end if;
      q    <= state;
      qbar <= not state;
    end if;
  end process p0;

end var;