------------------------------------------------------------------------------- -- Title : single board system using rs_cpu -- Project : ------------------------------------------------------------------------------- -- File : sbc.vst -- Author : -- Company : FoCEMS, UWE -- Last update: 2003/11/24 -- Platform : Alliance 5.0 on GNU/Linux ------------------------------------------------------------------------------- -- Description: top level integration of cpu & memory ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2003/11/02 1.0 ngunton Created ------------------------------------------------------------------------------- entity sbc is port ( clk : in bit; reset1 : in bit; reset2 : in bit; vdd : in bit; vss : in bit; a_bus : out bit_vector(15 downto 0); d_bus : out bit_vector(7 downto 0)); end sbc; architecture board_level of sbc is component cpu -- main cpu port ( address_bus : out bit_vector(15 downto 0); data_bus : inout mux_vector(7 downto 0) bus; read_m : out bit; write_m : out bit; clk : in bit; reset1 : in bit; reset2 : in bit; vdd : in bit; vss : in bit); end component; component cpu_ram port ( clk : in bit; reset : in bit; c_select : in bit; r : in bit; w : in bit; data_bus : inout mux_vector(7 downto 0) bus; addr_bus : in bit_vector(3 downto 0); vdd : in bit; vss : in bit); end component; component board_rom port ( r : in bit; c_select : in bit; addr_bus : in bit_vector(5 downto 0); data : out mux_vector(7 downto 0) bus; vdd : in bit; vss : in bit); end component; component buf_x2 PORT ( i : in BIT; q : out BIT; vdd : in BIT; vss : in BIT); end component; component inv_x2 port ( i : in BIT; nq : out BIT; vdd : in BIT; vss : in BIT); end component; signal addr_bus : bit_vector(15 downto 0); signal data_bus : mux_vector(7 downto 0) bus; signal r, w,n_cs : bit; begin -- board_level cpu : cpu port map ( address_bus => addr_bus, data_bus => data_bus, read_m => r, write_m => w, clk => clk, reset1 => reset1, reset2 => reset2, vdd => vdd, vss => vss); ----------------------------------------------------------------------------- -- data segment mapped to 0x0100 ----------------------------------------------------------------------------- data_seg : cpu_ram port map ( clk => clk, reset => reset1, c_select => addr_bus(8), r => r, w => w, data_bus => data_bus, addr_bus => addr_bus(3 downto 0), vdd => vdd, vss => vss); ------------------------------------------------------------------------------- -- rom mapped to 0x0000 with 1 bit address decode of addr_bus (8) low only. -- ie if address is 0x0100 then deselect ----------------------------------------------------------------------------- code_seg : board_rom port map ( r => r, c_select => n_cs, addr_bus => addr_bus(5 downto 0), data => data_bus, vdd => vdd, vss => vss); ----------------------------------------------------------------------------- -- invert address(8) to select rom ----------------------------------------------------------------------------- rom_select: inv_x2 port map ( i => addr_bus(8), nq => n_cs, vdd => vdd, vss => vss); ------------------------------------------------------------------------------- -- temporary fix to try and get the wiring shown correctly by xsch ------------------------------------------------------------------------------- b0: buf_x2 port map ( i => addr_bus(0), q => a_bus(0), vdd => vdd, vss => vss); b1: buf_x2 port map ( i => addr_bus(1), q => a_bus(1), vdd => vdd, vss => vss); b2: buf_x2 port map ( i => addr_bus(2), q => a_bus(2), vdd => vdd, vss => vss); b3: buf_x2 port map ( i => addr_bus(3), q => a_bus(3), vdd => vdd, vss => vss); b4: buf_x2 port map ( i => addr_bus(4), q => a_bus(4), vdd => vdd, vss => vss); b5: buf_x2 port map ( i => addr_bus(5), q => a_bus(5), vdd => vdd, vss => vss); b6: buf_x2 port map ( i => addr_bus(6), q => a_bus(6), vdd => vdd, vss => vss); b7: buf_x2 port map ( i => addr_bus(7), q => a_bus(7), vdd => vdd, vss => vss); b8: buf_x2 port map ( i => addr_bus(8), q => a_bus(8), vdd => vdd, vss => vss); b9: buf_x2 port map ( i => addr_bus(9), q => a_bus(9), vdd => vdd, vss => vss); ba: buf_x2 port map ( i => addr_bus(10), q => a_bus(10), vdd => vdd, vss => vss); bb: buf_x2 port map ( i => addr_bus(11), q => a_bus(11), vdd => vdd, vss => vss); bc: buf_x2 port map ( i => addr_bus(12), q => a_bus(12), vdd => vdd, vss => vss); bd: buf_x2 port map ( i => addr_bus(13), q => a_bus(13), vdd => vdd, vss => vss); be: buf_x2 port map ( i => addr_bus(14), q => a_bus(14), vdd => vdd, vss => vss); bf: buf_x2 port map ( i => addr_bus(15), q => a_bus(15), vdd => vdd, vss => vss); ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- hack to do the same for the data bus ------------------------------------------------------------------------------- d0: buf_x2 port map ( i => data_bus(0), q => d_bus(0), vdd => vdd, vss => vss); d1: buf_x2 port map ( i => data_bus(1), q => d_bus(1), vdd => vdd, vss => vss); d2: buf_x2 port map ( i => data_bus(2), q => d_bus(2), vdd => vdd, vss => vss); d3: buf_x2 port map ( i => data_bus(3), q => d_bus(3), vdd => vdd, vss => vss); d4: buf_x2 port map ( i => data_bus(4), q => d_bus(4), vdd => vdd, vss => vss); d5: buf_x2 port map ( i => data_bus(5), q => d_bus(5), vdd => vdd, vss => vss); d6: buf_x2 port map ( i => data_bus(6), q => d_bus(6), vdd => vdd, vss => vss); d7: buf_x2 port map ( i => data_bus(7), q => d_bus(7), vdd => vdd, vss => vss); end board_level;