library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity ram is
  port( clk, w : in  std_logic;
        adr     :     std_logic_vector(3 downto 0);
        i0      : in  std_logic_vector(7 downto 0);
        o0      : out std_logic_vector(7 downto 0)
        );
end ram;

architecture rtl_1 of ram is
  type my_array is array (0 to 15) of std_logic_vector(7 downto 0);
  signal s : my_array;
begin
  process(clk)
  begin
    if(rising_edge(clk)and w = '1') then
      s(to_integer(unsigned(adr))) <= i0;
    end if;
    
  end process;
  o0 <= s(to_integer(unsigned(adr)));
end rtl_1;