library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity downcount is
  
  generic (
    n : natural := 8;
    c : natural := (2**8)-1);

  port (
    clk     : in  std_logic;
    reset   : in  std_logic;
    load    : in  std_logic;
    preload : in  std_logic_vector(n-1 downto 0);
    count   : out std_logic_vector(n-1 downto 0));

end downcount;

architecture rtl of downcount is

  signal count_val :  unsigned(n-1 downto 0);

begin  -- rtl

  -- purpose: model of an n bit down counter with preload.
  -- type   : sequential
  -- inputs : clk, reset, load, preload,
  --        : active low reset and load.
  -- outputs: count


  -- to convert to an up counter: replace c with 0 in the
  -- reset initialisation and replace the minus with a plus)
  -- in the increment.


  
  p0: process (clk,reset,load)

  begin  -- process

    if (clk = '1' and not clk'stable) then  -- rising clock edge
      if reset = '0' then
        count_val <= to_unsigned(c,n);
                              -- to_unsigned(arg, size)
                              -- returns vector(size-1 downto 0)
                              -- used to set counter to all ones
      elsif load = '0' then
        count_val <= unsigned(preload);
      else
        count_val <= count_val - (to_unsigned(1,n));
      end if;
    end if;
  end process p0;

  count <= std_logic_vector(count_val);    

end rtl;