Co-requisites : None

Co-requisites [other]: None

Excluded combinations : None

Valid from : September 2000

AIMS:

This module aims to

• Extend the students understanding of the use of high level language approaches to hardware design.

• Provide practical experience of the complete design life cycle for Complex Programmable Logic Devices (CPLDs)

• Create opportunities for students to apply and critically assess their knowledge of current design and development techniques used in Real-Time systems/embedded systems fields.

• To allow student teams to complete an analysis and critical appraisal of the interaction between the high level design and the actual implementation of their designs.

LEARNING OUTCOMES:

The student will be able to:

• extend their intellectual, collaborative and practical skills throughout the module by focusing on the analysis and implementation of design techniques and methods. These skills will be used to develop novel solutions to the case study.

• design complex real-time systems, in teams, using selected techniques, implement them using VHDL and discuss the relative merits of each teams design.

• critically review the need for, and develop, comprehensive test harnesses for their VHDL designs.

• demonstrate confidence in the use and evaluation of simulation software for VHDL designs.

• critically review the use of VHDL synthesis, its advantages and disadvantages.

• analyse the hardware constraints such as performance, reliability and scale using techniques appropriate to real-time systems design.

• have developed their design from initial specification to tested hardware with minimum guidance.

SYLLABUS CONTENT:

• Review of VHDL language constructs

• Logic elements I. CMOS(combinational & sequential)

• Logic Elements II. Programmable ASIC. These two units will cover silicon level issues including timing, drive strength, effect on VHDL libraries, power requirements.

• Logic Elements III. Programmable I/O cells.

• Inside the VHDL design environment and design process.

• Use of modelling guidelines.

• Design Verification & formal verification of testing

• Simulation & testing, Test pattern generation.

• Controlling the synthesis process, optimisation.

• Timing.

• Constraints imposed by target hardware.

• Vendor specific issues.

• Hardware testing & debugging, faults, fault simulation, problems.

LEARNING APPROACHES:

Although the module will pursue a predominantly practical approach, with weekly lectures used to present the formal aspects of the material, opportunity will be provided for discussion sessions between the student teams.

The practical sessions will be based upon a case study. This will be typically a control system such as a trainer for a 'pick and place' robot arm or an interface for a serial bus such as the i²c bus. The students will work in design teams to complete the design and testing from initial requirements to final hardware.

INDICATIVE BIBLIOGRAPHY:

Smith, M.J.S. Application Specific Integrated Circuits Addison Wesley 1998

Sinander, P. VHDL Modelling Guidelines, European Space Agency, 1994

Skahill, K. VHDL for Programmable Logic, Addison Wesley, 1996.

Wakerly, J.F. Digital Design, Principles &. Practices, 3rd Ed.

Selected Lattice Semiconductor Corp. Technical documents.

ASSESSMENT

• FIRST ASSESSMENT FORMAT:

Component A Relative weighting in relation to the module as a whole _1_

Element 1 Relative weighting _1_

Exam.

Component B Relative weighting in relation to the module as a whole _3_