Shift Register :      15

architecture DataFlow OF Shifter is
    signal resultint : Std_Logic_Vector(n-1 downto 0) ;

begin
  shift: process (clk)
  begin  -- process shift
    if rising_edge(clk) then
      if shift_left then
        resultint <= shl( A, 1 );     
      elsif shift_right then
        resultint <=  shr( A, 1 );      
      end if;
    end if;
  end process shift;
  result <= resultint;
end DataFlow;