Register Architecture, enabled+tristate : 8

  process (ck)
  begin 
    if (rising_edge(ck) and en = '1') then
      q_sig <= a;
    end if;
  end process;
  process(w_en,q_sig)
  begin
   if (w_en) then d_ff_out <= q_sig;
   else d_ff_out <= 'Z';
   end if;  
  end process;