Register Architecture, works:       4

 architecture rtl_1 of d_ff is
  begin
   process( ck, a )
   begin
     if (rising_edge(ck)) then 
       d_ff_out <= a;
     end if;
   end process;
  end rtl_1;

Specifying a clock edge allows synthesis but may cause simulation problems as every change on 'a' causes re-evaluation of the process.