CPU Architecture : Control Signals 2


PCLOAD = JMP1
PCINC  = FETCH2
DRLOAD = FETCH2 \/ ADD1 \/ AND1
ACLOAD = ADD2 \/ AND2
ACINC  = INC1
IRLOAD = FETCH3

MEMBUS = FETCH2 \/ ADD1 \/ AND1
PCBUS  = FETCH1
READ   = FETCH2 \/ ADD1 \/ AND1