ASM to VHDL State Machines :                              6


  n3 <= reset and ((not p3 and not p2 and 
                   not p1 and not p0 
                   and turn(1))
        or (p3 and not p2 and not p1) 
        or (p3 and not p2 and p0));
  n2 <= reset and (p3 and not p1 and 
                   not p0);
  n1 <= reset and (not p2 and p0);
  n0 <= reset and ((not p3 and not p2 and 
                    not p1 and turn(0))
        or (not p3 and not p2 and not p1 
            and p0));