VHDL Syntax :        Models 4



a ROM

architecture rtl_1 of rom is
 subtype my_word is std_logic_vector
                     (7 downto 0);
 type my_array is array(0 to 63) of my_word;
 constant s : my_array := ( "00001011",
                            "00000010",
                            "00010001",
                            "00000001",

This example is obviously incomplete.