VHDL Syntax :         Models


All Vhdl models have two parts : an entity

entity and2 is
port (x, y : in   bit ;
z    : out  bit);
end entity and2 ;

This is a black box' description of our model, it describes the names, types and directions of ports. It tells us nothing about the internals of our model.

It is very important that the entity name 
matches the file name
is all in lower case letters.