VHDL Syntax :        language constraints


should be 15 characters or less
signal internal_trap_properly_received 
should not be confusing
signal BaudRateCounter
and
signal Baud_Rate_Counter
which are different identifiers
BUT !!!!
signal Baud_Rate_Counter
and
signal baud_rate_counter
ARE THE SAME IDENTIFIER TO THE COMPILER
vHDl iS nOT cASe SenSITivE At aLl
unix based tools are !