VHDL Examples : variables and addition.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...

p0 : process(clk, reset) is
  variable ct : unsigned(n-1 downto 0);

  begin
     if reset = '1' then
       ct := (others => '0');
     elsif rising_edge(clk) then
       ct := ct + 1; 
     end if;
     count <= std_logic_vector(ct);
end process;
...