CPU architecture & VHDL

entity vs_cpu is

  port (
    incount  : in  bit_vector(3 downto 0);
    ld_cnt   : out bit;
    inc_cnt  : out bit;
    clr_cnt  : out bit;
    arload   : out bit;
    pcload   : out bit;
    pcinc    : out bit;
    drload   : out bit;
    acload   : out bit;
    acinc    : out bit;
    irload   : out bit;
    alusel   : out bit;
    membus   : out bit;
    pcbus    : out bit;
    drbus    : out bit;
    read_mem : out bit);

end vs_cpu;




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