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Timetable 2011 - 2012.

Cycling in Bristol.

Propaganda.

 
  Module outline UFMFE8-30-2:

This page is currently being updated to reflect the transition from a 20 credit to a 30 credit module and the change in software tools from Alliance to Altera Quartus. Legacy material will be moved to an archive page.

This module provides a grounding in the use of the hardware description language, VHDL, along with an introduction to the architecture of microprocessors from a hardware designers perspective. The purpose of considering CPU architecture is to use it as an exemplar of complex digital design. We will cover the subset of VHDL that is used for synthesis with some reference to the use of the language for the behavioural modelling of hardware systems.

Your understanding and use of state-machines will be extended and the concept of a datapath-controller model introduced and developed. A series of problems will be explored culminating in the design, simulation,testing and, hopefully, implementation of a simple 8 bit microprocessor.

The design of the microprocessor control unit will be investigated in some detail with three distinct design approaches being covered.

The module uses Altera Quartus along with the simulator Modelsim ASE. Free to use versions are available from here. Make sure that you obtain the same version as that used in the lab, currently 11.0.

Most of the examples provided come from one of three sources: the recommended course texts, the documentation provided with the Alliance and Altera toolkits, or locally.

Timeline for labs and lectures, coursework deadlines UWE weeks 17 and 36
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Reading Strategy

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  Reading Strategy:

Unfortunately there is no single textbook that covers all the material in this module. Key material is made available via Blackboard The key material is to be found in the following books. A detailed cross-reference between lecture topics and book chapters or sections is given here. first 2 provide excellent coverage of VHDL in digital design as well as examples of implementing a CPU in VHDL. The third book has excellent coverage of the design issues in developing a CPU but minimal coverage of VHDL.

The following texts are also available from the library, Ashenden is available as an e-book as well as hard copy.

I strongly recommend Digital Design (VHDL), Ashenden, P

An alternative recommended text for VHDL is Digital System Design with VHDL, Zwolinski, M. You should read chapters 3 - 7 at a minimum.

Computer Systems, Organization & Architecture, Carpinelli, J., Addison-Wesley. Ideally you should read chapters 3, 5 - 8, 10. At the very least read chapter 6 available here and chapter 7 which is available via blackboard. Carpinelli's book is very expensive so I don't recommend purchasing it new. There are a few copies in the Bolland Library but demand tends to be high.

Blackwell reading list and bookshop availability.

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  Free Books:

For free books (provided you return them on time) on all aspects of VHDL and digital design, use the Library. A selection of suggested reading is given here.

  • Recommended course texts :
    • Digital Design, An Embedded Systems Approach, P.J.Ashenden: 621.3916 ASH
    • Computer Systems Organization & Architecture, J.D. Carpinelli: 004.22 CAR
    • Digital System Design with VHDL, M. Zwoliński: 621.392 ZWO
  • For general discussions of Digital Design Concepts. Both are useful 'cookbooks' for digital design and have online support material. Wakerly's book also contains a section on VHDL. There are many other books on digital design in the Library.
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  Lecture Slides
New stuff Watch this video on CPU design from hardware hacker byterazor

Examples are taken/modified from the recommended course texts

Lecture recordings here



The sequence enumeration article

Sequence enumeration lecture handout

A short article on ASM (in postscript) from Circuit Cellar Magazine.


Altera Quartus coding guidelines. Note that the reference to using templates requires the built-in editor

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  Laboratory worksheets & Exercises :

Use them well. Note that each lab will require several weeks work.


DE0 User Manual with pin configuration information
  • Lab 1 :
    • Worksheet 0 on using the editor. It is essential that you do this worksheet. You might need to follow the instructions below (new start-up script) if your .emacs file doesn't look like the example in the worksheet.
    • it should say 'vhdl mode' on a bar at the bottom of the editor.
    • Worksheet 1 introducing the tools and a little of the language. Ignore references to the Alliance tookit.
    • Worksheet 2 introducing a little more of the language.
  • Lab 2 :
    • Air-conditioning exercise using behavioural and state-machine techniques
    • Rotation sensor state machine worksheet Design, implement, verify...
    • state machines worksheet in VHDL. Note that the path to the example refered to in the worksheet is temporarily here
  • Lab 3 :
    • Datapath-controller development exercise 1, railway crossing using multiple state-machines
    • Datapath-controller development exercise 2 traffic-lights problem.
      • Using the traffic-lights worksheet as your specification: implement a controller which will manage a set of timers.
      • You should use ASM notation for your design.
      • Example code for quartus state machine
      • Implement and test the controller.
      • Implement the timer(s).
      • Combine them into a top level design.
      • Verify your top level design.
      • Modify to run on the DE0 board.
    • Datapath-controller development exercise 3 structural models or putting it all together.
    • Example code for VSCPU hard-wired controller
  • Lab 4: Optional
    • Redesign your traffic light controller as either a hardwired controller or as a microsequencer. You only need to do the design, not the implementation
  • Lab 5 ... Implementation of CPU as per assignment specification
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  Worksheets for Labs & related support material:
  • CPU exercise related
    • Register with increment, tri-state outputs.
    • synchronous downcounter with load. Demonstrates use of generics and functions. Modify to make the registers.
    • PDF showing the RSCPU with multiplexors instead of tristates.
    • 3 to 8 decoder example
    • Example .do file showing automated verification, storing results in a file and all done using tcl. The example is for a microsequencer based control unit.
    • TCL in Modelsim , an extract from the Modelsim user manual that provides a syntax summary and examples.
    • A few rough notes on extending the RS-CPU instruction set by using the top 4 bits as fields to select the addressing mode and branch consition code or register. Notes, tables.
  • Misc. VHDL
    • Thunderbird lights outline sum of products state machine in vhdl.
    • Behavioural model of a toggle flip-flop showing use of variables in VHDL.
    • Discussion of state value assignment using the toll booth example.
  • Emacs support worksheets
  • Misc Support Worksheets
    • RCS worksheet...(also under construction)
    • tar related worksheet if you're stuck unpacking the Alliance stuff
    • example shell script for running the alliance toolchain
D-type flipflop worksheet exploring timing issues.
Overview of delta delay in simulation
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  Code and Pattern examples:

Last year's Exam paper

Other stuff


RS_CPU in real hardware

Support files for an SBC version of the RS_CPU, edit to suit your design. The top level model includes the address decoding logic to suit the memory map described in the ROM file.

A work in progress on writing pattern files. This example is for the Alliance toolkit. A similar approach is required for writing .do files for Modelsim. Start with your vhdl and walk through it making a note of what value inputs need to be in order to trigger a particular behaviour. Make a note of what you expect the output to be. Then write your pattern file using this information. You might find this timing font useful.

Implementation of the RS_CPU using the Altera Quartus software. If you want to have a look then download this Quartus project archive to a new folder and open it in Quartus. It is an implementation of the CPU only

A .do file for the RS_CPU

A complete system including ROM with boot code, an executable programme and memory mapped I/O here.

This is untested after porting to the new DE0 boards.

Both the above projects will need the pins to be mapped to the target boards. See the DE0 documentation for details.

Other soft-core CPUs

A selection of alternative CPU designs that you might like to have a look at.

  • These two chapters provide an insight into arithmetic and logic in RTL and a simple processor designed by M. Morris Mano. Note: I am aware that there is a VHDL implementation floating about on the interweb.
  • The Parwan CPU from Navabi's book refered to above.
  • The Apollo Guidance computer. Fly to the Moon and back on a 12k ROM based system.
  • The gumnut processor documented in Ashenden's book, see above for book details or here for the books companion site
  • A custom processor developed for a space beacon at St. Louis University.
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Bus protocols

References to the various bus protocols mentioned in the lecture.



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New stuff


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Hints'n'tips on setting up your environment in the lab

'dot emacs'

Additions to setup vhdl mode for the Alliance toolkit file extensions. Copy and paste the following into your .emacs file :-


(autoload 'vhdl-mode "vhdl-mode" "VHDL Editing Mode" t)
(setq auto-mode-alist
(append
'(("\\.vhd$" . vhdl-mode)
("\\.vbe$" . vhdl-mode)
("\\.vst$" . vhdl-mode)
("\\.fsm$" . vhdl-mode)
) auto-mode-alist))


To avoid the problem, in 3P28, of Emacs entering 'diff-mode' when opening pattern files (.pat), add the following to your .emacs file:



(autoload 'text-mode "text-mode" "Text Editing Mode" t)
(setq auto-mode-alist
(append
'(("\\.pat$" . text-mode)
) auto-mode-alist))

patch -i xpat.patch xpat.par

xpat.par is in $ALLIANCE_TOP/etc. save the patch file as plain text and apply. You will need write permission on both the .par file and it's directory.

Alternatively, copy the xpat.par file to your home directory, modify as above and then set the environment variable XPAT_PARAM_NAME to point to the file in your home directory eg

export XPAT_PARAM_NAME=$HOME/xpat.par

Add this to your start-up files (.bashrc / .bash_profile for bash and related shells) to avoid having to set it manually every time you log in.


import -rotate -90 -page a4 filename.[ ps | eps | jpeg | png ]

in a terminal and then drag a bounding box to surround the area to be captured. The above will rotate the captured area and fit it to an a4 sized sheet. The output file will be in the format specified by the output file suffix and selected from the list above.


Examples are in a tarball for download. Save this file to a temporary directory, cd into the temporary directory and then type tar -zxvf startups.tar.gz. This will unpack the files and avoid overwriting your existing files. you can then copy the bits that you want into your existing files. Alternatively just cut'n'paste from the browser window :)

There are all sorts of odds'n'ends in the tarball most of which yo probably don't need to worry about at this stage

Also included in the download are a basic .emacs to extend the list of filenames which will trigger vhdl mode and a .bashrc to set up the environment variables for the Alliance toolset amongst other things.


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Sample Q's

here, note that more emphasis will be placed on ASM as a diagramatic representation of state machines this year than in the papers from which the questions are taken.

Reference Material

ASM examples and explanations. oldish but useful discussion of ASM with FPGA & CPLD emphasis.
Archive of VHDL links, tutorials, software and related material. A good starting point.
Excellent VHDLtutorial site.


Sequence Enumeration : Developing Black Box Specifications
Sequence Enumeration : Soda Machine example.

Rules for the soda machine example

Derived rules for the soda machine example

isp1016 device data sheet

74LS74 D-type flip-flop data sheet for use with 'd-type' worksheet.

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